3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
The K4M513233C is 536,870,912 bits synchronous high data rate
Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated
with SAMSUNG high performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock and I/O
transactions are possible on every clock cycle. Range of operating
frequencies, programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of high bandwidth
and high performance memory system applications
• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 90Balls FBGA
ispMACH 4000V,B,C,Z Family
ispMACH 4000 Brochure
Integrated Circuits (ICs)
Embedded - CPLDs (Complex Programmable Logic Devices)
In System Programmable
Delay Time tpd(1) Max
Voltage Supply - Internal
3 V ~ 3.6 V
Number of Logic Elements/Blocks
Number of Macrocells
Number of Gates
Number of I /O
0°C ~ 90°C
Package / Case
Supplier Device Package
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LC4128V-75TN100C In-System Programmable SuperFAST High Density PLDs